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| No. | Topic | Project No. | PDF Download |
| 173 | C.-C. Wang, L S S P. K. Chodisetti, J.-Y. Ke, C.-Y. Lo, T.-J. Lee, and L. K. S. Tolentino, "A 6-Gbps 16-nm FinFET CMOS I/O buffer with variation insensitivity ensured by genetic algorithm," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 71, no. 11, pp. 4961-4972, Nov. 2024. DOI : 10.1109/TCSI.2024.3419020 | NSTC 112-2218-E-110-005- |
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| 172 | C.-C. Wang, L S S P. K. Chodisetti, B.-H. Liao, P. Vellanki, T.-J. Lee, “A 1-6.5 Gbps dual-loop CDR design with coarse-fine tuning VCO and modified DQFD,” Microelectronics Journal,vol. 151, pp. 1-15, Sep. 2024. https://doi.org/10.1016/j.mejo.2024.106355 | NSTC 112-2221-E-110-063-MY3 |
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| 171 | C.-C. Wang, L S S P. K. Chodisetti, D. S. Kamarajugadda, O. L. J. A. Jose, and P. Vellanki, “A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single- phase all-N-transistor logic,” Integration, the VLSI Journal, vol. 98, pp. 1-8, Sep. 2024. https://doi.org/10.1016/j.vlsi.2024.102234 | NSTC 112-2221-E-110-063-MY3 |
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| 170 | C.-H. Yeh, Y.-W. Lai, Y.-Y. Lin, M.-J. Chen, C.-C. Wang, “Underwater image enhancement based on light field-guided rendering network,” Journal of Marine Science and Engineering, pp. 1-12, July 2024. https://doi.org/10.3390/jmse12071217 | Download | |
| 169 | C.-C. Wang, L S S P. K. Chodisetti, P.-Y. Lou, C.-C.-H. Hung, P. Vellanki, R. G. B. Sangalang, L. K. S. Tolentino, T. A. Ronquillo “A single-chip PFM-controlled LED driver with 0.5% illuminance variation,” Microelectronics Journal, vol. 147, May 2024. DOI: 10.1016/j.mejo.2024.106167 | NSTC 112-2221-E-110-063-MY3 | Download |
| 168 | O. L. J. A. Jose, V. N. Kolakaluri, R. G. B. Sangalang, L. K. S. Tolentino, and C.-C. Wang "A 6.25 MHz 3.4 mW single clock DPWM technique using matrix shift array,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 5, pp. 972 - 976, published on line, Feb. 2024. DOI: 10.1109/tvlsi.2024.3367300 | NSTC 111-2623-E-110-002- |
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| 167 | C.-C. Wang, L. K. S. Tolentino, S.-W. Lu, R. G. B. Sangalang, O. L. J. A. Jose, and T.-J. Lee, “A metastable RNG using interleaved NAND- and NOR-based TEROs,” International Journal of Electronics Letters, published on lien, Feb. 2024. (DOI : 10.1080/21681724.2024.2312551) |
NSTC 109-2218-E-110-007- |
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| 166 | C.-C. Wang, O. L. J. A. Jose, L. Lin, L. K. S. Tolentino, R. G. B. Sangalang, and A. L. Salvador, “A 13.73 ns input time range TDA design based on adjustable current sources using 40-nm CMOS process,“ Circuits, Systems, and Signal Processing, vol. 43, pp. 3376-3395, published on line, Mar. 2024. DOI : 10.1007/s00034-024-02640-2 | NSTC 110-2224-E-110-004 |
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| 165 | R. G. B. Sangalang, S. Reddy, L. K. S. Tolentino, Y.-W. Shen, O. L. J. A. Jose, and C.-C. Wang, "A 210-MHz 4.23 fJ energy/bit 1-kb asymmetrical Schmitt-trigger-based SRAM Using 40-nm CMOS Process," IEEE Trans. on Circuits & Systems - II (TCAS-II), (early access), June 2023. (https://doi.org/10.1080/00207217.2023.2235720) | MOST 110-2221-E-110-063-MY2 |
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| 164 | C.-C. Wang, L. K. S. Tolentino, P.-C. Chen, R. G. B. Sangalang, and O. L. J. A. Jose, “A 92.95%-efficiency high voltage dual-mode buck converter using 0.5-um HV CMOS process,” International Journal of Electronics, published on line, July 2023. (https://doi.org/10.1080/00207217.2023.2235720) | MOST 109-2218-E-110-007- |
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| 163 | C.-C. Wang, L. K. S. Tolentino, H.-C. Wu, R. G. B. Sangalang, O. L. J. A. Jose, and T.-H. Lin, “A negative voltage generator with 4-stage configurable parallel switching,” International Journal of Electronics Letters, pp. 361-379, Jul. 2023. (https://doi.org/10.1080/21681724.2023.2224067) | NSTC 110-2218-E-110-008- |
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| 162 | C.-C. Wang, L. K. S. Tolentino, S.-W. Lu, O. L. J. A. Jose, R. G. B. Sangalang, T.-J. Lee, P.-Y. Lou, W.-C. Chang, “A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process,” Integration, the VLSI Journal,Vol. 90, pp. 245-260, , May 2023. | NSTC 108-2218-E-110-002- |
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| 161 | C.-C. Wang, R. G. B. Sangalang, I.-T. Tseng, Y.-J. Chiu, Y.-C. Lin, and O. L. J. A. Jose, "A 1.0 fJ energy/bit single-ended 1-kb 6T SRAM implemented using 40-nm CMOS process," IET Circuits, Devices & Systems, pp. 1–13, Jan. 2023. (https://doi.org/10.1049/cds2.12141) | MOST 109-2218-E-110-007 |
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| 160 | C.-C. Wang, R. G. B. Sangalang, C.-P. Kuo, H.-C. Wu, Y. Hsu, S.-F. Hsiao, and C.-H. Yeh, "A 40.96-GOPS 196.8-mW digital logic accelerator used in DNN for underwater object recognition," IEEE Trans. on Circuits and Systems I: Regular Papers,vol. 69, no. 12, pp. 4860-4871, Dec. 2022. (DOI: 10.1109/TCSI.2022.3187450) | MOST110-2221-E-110-063-MY2 |
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| 159 | C.-H. Yeh, C.-H. Lin, L.-W. Kang, C.-H. Huang, M.-H. Lin, C.-Y. Chang, and C.-C. Wang, “Lightweight deep neural network for joint learning of underwater object detection and color conversion,” IEEE Trans. on Neural Networks and Learning Systems, vol 33, no. 11, pp. 6129-6143, Nov. 2022. (DOI : 10.1109/TNNLS.2021.3072414) | MOST 109-2218-E-110 -007 - |
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| 158 | C.-C. Wang, O. L. J. A. Jose, W.-S. Yang, R. G. B. Sangalang, L. K. S. Tolentino, and T. -J. Lee, “A 16-nm FinFET 28.8-mW 800-MHz 8-bit all-N-transistor logic carry look-ahead adder,” Circuits, Systems, and Signal Processing, Oct. 2022. (DOI: https://doi.org/10.1007/s00034-022-02212-2) | MOST 109-2218-E-110-007- |
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| 157 | P.-Y. Lou, Y.-Y. Ho, C.-C. Wang, and W.-C. Chang, “Analysis of layout arrangement for CMOS oscillators to reduce overall variation on silicon,” Advances in Science, Technology and Engineering Systems Journal (ASTESJ), vol. 7, no. 5, pp. 46-52, Oct. 2022. (DOI : http://dx.doi.org/10.25046/aj070507) | Download | |
| 156 | C.-C. Wang, R. G. B. Sangalang, M.-J. Wu, T.-J. Lee, Y.-J. Chen, L. K. S. Tolentino, and O. L. J. A. Jose, “A 2.71 fJ/conversion-step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems,” International Journal of Electronics, (early access on line), Sep. 2022. (https://doi.org/10.1080/00207217.2022.2118861) | MOST 110-2218-E-110-008- |
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| 155 | C.-C. Wang, L. K. S. Tolentino, U. K. N. Ekkurthi, P.-Y. Lou, and S. Sampath, “A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process,” Inter. Journal of Electronics Letters, (early access on line), June 2022. (https://doi.org/10.1080/21681724.2022.2087912) | MOST 110-2218-E-110-008- |
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| 154 | P.-Y. Lou, Y.-X. Chen, C.-C. Wang, and W.-C. Chang, “A CMOS on-chip high-precision PVTL detector,” Advances in Science, Technology and Engineering Systems Journal (ASTESJ), vol. 7, no. 3, pp. 87-94, May 2022. (DOI : http://dx.doi.org/10.25046/aj070310) | Download | |
| 153 | C.-C. Wang, O. L. J. A. Jose, P.-Y. Lou, C.-J. Hsu, L. K. S. Tolentino, and R. G. B. Sangalang, “Single-chip DC-DC buck converter design based on PWM with high-efficiency in light load,” International Journal of Electronics Letters, (early access on line), May 2022. (DOI: 10.1080/21681724.2022.2068661) | MOST 109-2241-E-110-001- |
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| 152 | C.-C. Wang, R. G. B. Sangalang, and I.-T. Tseng, "A single-ended low power 16-nm FinFET 6T SRAM design with PDP reduction circuit," IEEE Trans. on Circuits & Systems - II (TCAS-II), vol. 68, no. 12, pp. 3478-3482, Dec. 2021. (DOI: 10.1109/TCSII.2021.3123676) | MOST 110-2218- E-110-008 |
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| 151 | C.-C. Wang, O. L. J. A. Jose, P.-K. Su, L. K. S. Tolentino, R. G. B. Sangalang, J. S. Velasco, and T.-J. Lee, “An adaptive constant current and voltage mode P&O-based maximum power point tracking controller IC using 0.5-µm HV CMOS,” Microelectronics Journal, Vol. 118, Dec. 2021, 105295 | MOST 109-2224-E-110-001 |
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| 150 | C.-C. Wang, L. K. S. Tolentino, C.-Y. Huang, and C.-H. Yeh, "A 40-nm CMOS multifunctional computing-in-memory (CIM) using single-ended disturb-free 7T 1Kb SRAM," IEEE Trans. on Very Large Scale Integration (VLSI) Systems,vol. 29, no. 12, pp. 2172 - 2185, Oct. 2021. (DOI: 10.1109/TVLSI.2021.3115970) | MOST 108-2218-E-110-002 |
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| 149 | C.-C. Wang, and C.-P. Kuo, “200-MHz single-ended 6T 1-kb SRAM with 0.2313 pJ energy/access Using 40-nm CMOS logic process,” IEEE Trans. on Circuits & Systems - II (TCAS-II), vol. 68, no. 9, pp.3163 - 3166 (DOI: 10.1109/TCSII.2021.3091973), Sep. 2021. | MOST 108-2218-E-110-011 |
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| 148 | C.-C. Wang, P.-Y. Lou, Z.-Y. Hou, and H.-C. Tsai, “0.7% error rate 3A bidirectional current sensor using high voltage CMOS process,” Microelectronics Journal, vol 114(105127), August 2021. (DOI = 10.1016/j.mejo.2021.105127) | MOST 110-2218-E-110-008- |
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| 147 | C.-C. Wang, L. K. S. Tolentino, P.-C. Chen, J. Hizon, C.-K. Yen, C.-T. Pan, Y.-H. Hsueh, “A 40-nm CMOS piezoelectric energy harvesting IC for wearable biomedical applications,” Electronics, 10(6), 649, Mar. 2021. (DOI : 10.3390/electronics10060649) | MOST 109-2224-E-110-001- |
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| 146 | C.-C. Wang, P.-Y. Lou, T.-Y. Tsai, I.-Y. Huang, Y.-C. Lin, T.-J. Lee, and G.-R. Chen, “High-accuracy impedance read-out circuit for BIA-type biomedical sensors,” Circuits, Systems, and Signal Processing, Mar. 2021. (DOI: 10.1007/s00034-021-01670-4) | MOST 109-2224-E-110-001- |
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| 145 | C.-C. Wang, “Tutorial : Design of high-speed nano-scale CMOS mixed-voltage digital I/O buffer with high reliability to PVTL variations,”IEEE Trans. on Circuits & Systems - II (TCAS-II), vol. 6, no. 2, pp. 562-567, Feb. 2021. (DOI : 10.1109/TCSII.2020.3041607) | MOST 107-2218-E-110-002 |
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| 144 | C.-C. Wang, P.-Y. Lou, T.-Y. Tsai, Y.-Y. Chou, and T.-J. Lee, “2×VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process,” Circuits, Systems, and Signal Processing, Nov. 2020. (DOI: 10.1007/s00034-020-01594-5) | MOST 108-2218-E-110-011- |
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| 143 | T.-J. Lee, S.-W. Huang, and C.-C. Wang, "A slew rate enhanced 2×VDD I/O buffer with precharge timing technique," IEEE Trans. on Circuits & Systems - II (TCAS-II), vol. 67, no. 11, pp. 2707-2711, Nov. 2020. (DOI: 10.1109/TCSII.2020.2967868) | MOST 108-2218-E-110-002- |
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| 142 | C.-C. Wang, K.-Y. Chao, S. Sampath, and P. Suresh, “Anti-PVT-variation low-power time-to-digital converter design using 90-nm CMOS process,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 2069-2073, Sep. 2020. | MOST 108-2218-E-110-002- |
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| 141 | M. Rif’an, R. Rieger, and C.-C. Wang, “Accurate RR-interval detection with daubechies filtering and adaptive thresholding,” Lect. Notes Electrical Eng., Advances in Electronics Engineering, vol. 619, pp. 59-67, Dec. 2019. (ISBN: 978-981-15-1288-9) | MOST 106-2221-E-110-058- |
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| 140 | C.-C. Wang, N. Sulistiyanto, T.-Y. Tsai, and Y.-H. Chen, “Multifunctional in-memory computation architecture using single-ended disturb-free 6T SRAM,” Lect. Notes Electrical Eng., Advances in Electronics Engineering, vol. 619, pp. 49-57, Dec. 2019. (ISBN: 978-981-15-1288-9) | MOST 107-2218-E-110-004- |
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| 139 | C.-C. Wang, Z.-Y. Hou, D.-S. Wang and C.-L. Hsieh, “A single-ended 28 nm CMOS 6T SRAM design with read-assist path and PDP reduction circuitry,” Journal of Circuits, Systems, and Computers (JCSC), vol. 29, no. 6, pp. 2050095-1~2050095-18, June 2020. (DOI : 10.1142/S0218126620500954) | MOST 108-2218-E-110-002- |
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| 138 | C.-C. Wang, Z.-Y. Hou, and Y.-L. Deng, “2-GHz 2xVDD 28-nm CMOS digital output buffer with slew rate auto-adjustment against process and voltage variations,” Journal of Circuits, Systems, and Computers (JCSC), vol. 29, no. 6, pp. 2050088-1~2050088-17, June 2020. (DOI : 10.1142/S0218126620500887) | MOST 106-2221-E-110-058- |
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| 137 | C.-C. Wang, P.-Y. Lou, T.-Y. Tsai, and H.-Y. Shih, "74-dBc 71-MHz 4-stage Pipeline ROM-less DDFS Using Factorized 2nd-order Parabolic Equations," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, (doi: 10.1109/TVLSI.2019.2925574, June 2019), vol. 27, pp. 2464-2468, Oct. 2019. | MOST 106-2221-E-110-058- |
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| 136 | C.-C. Wang, N. Sulistiyanto, H.-Y. Shih, Y.-C. Lin, W. Wang, “Power-effective ROM-less DDFS design approach with high SFDR performance,” Journal of Signal Processing Systems, doi: 10.1007/s11265-019-01460-x, May 2019. | MOST 107-2218-E-110-004- |
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| 135 | C.-C. Wang, Z.-Y. Hou, and J.-C. You, “Temperature-to-frequency converter with 1.47% error using thermistor linearity calibration,” IEEE Sensors Journal, vol. 19, no. 13, pp. 4804-4811, July 2019. | MOST 107-2218-E-110-004- |
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| 134 | T.-J. Lee,T.-Y. Tsai, W. Lin, U.-F. Chio, and C.-C. Wang “A slew rate variation compensated 2xVDD I/O buffer using deterministic P/N-PVT variation detection method ,” IEEE Trans. on Circuits & Systems - II (TCAS-II), vol. 66, no. 1, pp. 116-120, Jan. 2019. | NSC-102-2221-E-110- 083-MY3 |
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| 133 | C.-C. Wang, D.-S. Wang, and S.-Y. Chen, "56.67 fJ/bit single-ended disturb-free 5T loadless 4 kb SRAM using 90 nm CMOS technology, " Analog Integrated Circuits and Signal Processing,vol. 96, no. 3, pp. 435-443, Sep. 2018. (DOI 10.1007/s10470-018-1186-5) | MOST 104-2622-E-006-040-CC2 |
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| 132 | C.-C. Wang, T.-Y. Tsai, and W. Lin, “A 90-nm CMOS 800 MHz 2xVDD output buffer with leakage detection and output current self-adjustment,” Analog Integrated Circuits and Signal Processing, (DOI 10.1007/s10470-018-1285-3), Aug 2018. | NSC-102-2221-E-110-083-MY3 |
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| 131 | C.-C. Wang, Z.-Y. Hou, and J.-C. You, “A high-precision CMOS temperature sensor with thermistor linear calibration in the (−5 °C, 120 °C) temperature range,” Sensors, (accepted, paper ID = sensors-318369), July 2018. | MOST 106-2221-E-110-065- |
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| 130 | C.-C. Wang, T.-Y. Tsai, Y.-L. Deng, and T.-J. Lee, “500 MHz 90-nm CMOS 2xVDD digital output buffer immune to process and voltage variations ,” Circuits, Systems, and Signal Processing,vol. 38, no. 2, July 2018. | MOST 105-2218-E-110-006 |
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| 129 | C.-C. Wang, Z.-Y. Hou, C.-L. Chen, D. Shmilovitz, “A lock detector loop for low-power PLL-based clock and data recovery circuits,” Circuits, Systems & Signal Processing, vol. 37, pp. 1692-1703, Mar. 2018. | NSC 102-2221-E-110-081-MY3 |
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| 128 | L.-J. Lan, C.-H. Hsieh, I.-Y. Huang, Y.-C. Lin, T.-Y. Tsai, and C.-C. Wang, “Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine,” Sensors, vol. 17, no. 12, pp. 2760-2771, Nov. 2017. | MOST 105-2622-E-006-018-CC2 |
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| 127 | D.-S. Wang, Y.-H. Su, and C.-C. Wang, " A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM," Microelectronics Journal, vol. 70, pp. 107-116, Nov. 2017. | MOST 104-2622-E-006-040-CC2 MOST 105-2218-E-110-006 MOST 105-2221-E-110-058 |
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| 126 | T.-J. Lee, T.-Y. Tsai, W. Lin, U.-F. Chio, and C.-C. Wang, “A dynamic leakage and slew Rate compensation circuit for 40-nm CMOS mixed-voltage output buffer,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp. 3166-3174, Aug. 2017. | NSC-102-2221-E-110-083-MY3 |
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| 125 | C.-C. Wang, Z.-Y. Hou, and K.-W. Ruan, “2 x VDD 40-nm CMOS Output Buffer with Slew Rate Self-adjustment Using Leakage Compensation,” IEEE Trans. on Circuits & Systems - II (TCAS-II), vol. 64, no. 7, pp. 812-816, July 2017. | NSC102-2221-E-110-081-MY3 |
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| 124 | W.-H. Huang, I.-Y. Huang, Y.-S. Tseng, C.-H. Hsieh, and C.-C. Wang, “A 19.38 dBm OIP3 Gm-boosted Up-conversion CMOS Mixer for 5-6 GHz Application,” Microelectronics Journal, vol. 60, no. C, pp. 38-44, Feb. 2017 | MOST 103-2221-E-110-083 |
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| 123 | C.-C. Wang, T.-Y. Tsai, T.-J. Lee, and K.-W. Ruan, “2xVDD output buffer with 36.4% slew rate improvement using leakage current compensation,” Electronics Letters, vol. 35, no. 2, pp. 62-64, Jan. 2017. | NSC 102-2221-E-110-083-MY |
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| 122 | C.-C. Wang, Z.-Y. Hou, W.-J. Lu, and S.-S. Wang, “High-voltage on-chip current sensor design and analysis for battery modules,” IET Circuits, Devices & Systems, vol. 10, no. 6, pp. 492–496, Nov. 2016. | NSC 102-2221-E-110-081-MY3 |
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| 121 | C.-C. Wang, D.-S. Wang, C.-H. Liao, and S.-Y. Chen, “A leakage compensation design for low supply voltage SRAM,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1761-1769, May 2016. | NSC 102-3113-P-110-101 |
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| 120 | C.-C. Wang, T.-Y. Tsai, W.-J. Lu, C.-L. Chen and Y.-L. Wu, "A 30 V rail-to-rail operational amplifier," Microelectronics Journal, vol. 46, pp. 911-915, Aug. 2015. | NSC101-3113-P-110-004 |
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| 119 | C.-C. Wang, W.-J. Lu, and T.-C. Wu, “Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring,”Microelectronics Journal, vol. 46, pp. 819-824, July 2015. | NSC 102-2221-E-110-081-MY3 |
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| 118 | C.-C. Wang, D.-S. Wang, T.-C. Sung, Y.-J. Hsieh, and T.-J. Lee, “A +/- 3.07% frequency variation clock generator implemented using HV CMOS process,” Microelectronics Journal, vol. 46, no. 4, pp. 285-290, April 2015. | NSC 102-3113-P-110-101 |
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| 117 | C.-C. Wang, C.-L. Chen, Z.-Y. Hou, Y. Hu, J.-W. Lee, W.-Y. Lin, Y.-F. Chang, C.-W. Hsu, and M.-H. Song, “A 60V tolerance transceiver with ESD protection for FlexRay-based communication systems,” IEEE Trans. on Circuits & Systems - I (TCAS-I), vol. 62, no. 3, pp. 752-760, Mar. 2015. | Download | |
| 116 | C.-C. Wang, D.-S. Wang, T.-C. Sung, Y.-H. Wu, and D. Shmilovitz, “A +/-10.5 V 16-channel programmable pulse generator using high-voltage BCD CMOS Process,” Electronics Letters, vol. 50, no. 24, pp. 1797-1799, Dec. 2014. | NSC 101-3113-P-110-004 |
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| 115 | C.-C. Wang, W.-J. Lu, and T.-Y. Tsai, “Analysis of calibrated on-chip temperature sensor with process compensation for HV chips,” IEEE Trans. on Circuits & Systems - II (TCAS-II), vol. 62, no. 3, pp. 217-221, Mar. 2015. | NSC 101-3113-P-110-004 |
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| 114 | C.-C. Wang, D.-S. Wang, T.-C. Sung, Y.-J. Hsieh, and T.-J. Lee, “Process corner detection by skew inverters for 500 MHz 2xVDD output buffer using 40-nm CMOS technology,” Microelectronics Journal, vol. 46, no. 1, pp. 1-11, Jan. 2015. | NSC
102-3113-P-110-101 |
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| 113 | C.-L. Chen, D.-S. Wang, J.-J. Li, and C.-C. Wang, “A voltage monitoring IC with HV multiplexer and HV transceiver for battery management systems,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, DOI: 10.1109/TVLSI.2014.2303989, vol 23, no. 2, pp. 244-253, Feb. 2015. | MOEA 102-EC-17-A-01-01-1010 |
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| 112 | D. Shmilovitz, S. Ozeri, C.-C. Wang, and B. Spivak, “Noninvasive control of the power transferred to an implanted device by an ultrasonic transcutaneous energy transfer link,” IEEE Trans. on Biomedical Engineering, vol. 61, no. 4, pp995-1004, April 2014. (10.1109/TBME.2013.2280460) | Download | |
| 111 | C.-C. Wang, C.-L. Chen, G.-N. Sung, C.-L. Wang, and C.-Y. Juan, “A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard,” J. of Signal Processing Systems,vol. 74, pp. 221-233, Feb. 2014. (DOI 10.1007/s11265-013-0779-6) | MOEA 101-EC-17-A-01-01-1010 |
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| 110 | C.-C. Wang, W.-J. Lu, C.-L. Chen, H.-Y. Tseng, R.-C. Kuo, and C.-Y. Juan, “A 2 × VDD Output Buffer with PVT Detector for Slew Rate Compensation” Microelectronics Journal, vol. 44, no. 5, pp. 393-399, May 2013. | Download | |
| 109 | C.-C. Wang , T.-C. Sung, C.-H. Hsu, Y.-D. Tsai, Y.-C. Chen, M.-C. Lee, and I-Y. Huang, “A protein concentration measurement system using a FPW frequency-shift readout technique,” Sensors, vol. 13, pp. 86-105, Jan. 2013. (doi:10.3390/s130100086) | NSC 99-2221-E-110-081-MY3 |
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| 108 | C.-C. Wang, C.-L. Chen, J.-J. Li, G.-N. Sung, T.-H. Yeh, and C.-Y. Juan, “A Low-Power Transceiver Design for FlexRay-based Communication Systems,” Microelectronics Journal, vol. 13, pp. 86-105, Jan. 2013. (doi:10.3390/s130100086) | MOEA 101-EC-17-A-01-01-1010 |
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| 107 | C.-C. Wang, C.-L. Chen, R.-C. Kuo, H.-Y. Tseng, J.-W. Liu, C.-Y. Juan, “On-chip process and temperature monitor for self-adjusting slew rate control of 2xVDD output buffers,” IEEE Trans. on Circuits & Systems - I : Regular Papers, vol. pp, no. 99, pp. 1-9, Jan. 2013 | MOEA 100-EC-17-A-01-1010 |
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| 106 | C.-C. Wang, C.-L. Chen, H.-Y. Tseng, H.-H. Hou, C.-Y. Juan, “A 800 Mbps and 12.37 ps jitter bidirectional mixed-voltage I/O buffer with dual-path gate-tracking circuit,” IEEE Trans. on Circuits & Systems - I : Regular Papers,vol. 60, no. 1, pp. 116-124, Jan. 2013 | MOEA 101-EC-17-A-01-1010 |
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| 105 | S.-H. Yang, and C.-C. Wang, “A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers,” Microelectronics Journal, vol. 43, no. 4, pp. 274-279, Apr. 2012. | NSC 99-2221-E-110-082-MY3 |
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| 104 | S.-H. Yang, and C.-C. Wang, “Feed-forward output swing prediction AGC design with parallel-detect singular-store peak detector,” Microelectronics Journal, vol. 43, no. 4, pp. 250-256, Apr. 2012. | NSC99-2221-E-110-082-MY3 |
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| 103 | I.-Y. Huang, M.-C. Lee, C.-H. Hsu, C.-C. Wang, “Development of a flexural plate-wave (FPW) Immunoglobulin-E (IgE) allergy bio-sensing microsystem,” Sensors & Actuators: B. Chemical, vol. 162, pp. 184-193, Mar. 2012. | MOEA 98-EC-17-A-19-S1-133 |
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| 102 | S.-H. Yang, J.-W. Liu, and C.-C. Wang, “A single-chip 60-V bulk charger for series Li-ion batteries with smooth charge-mode transition,” IEEE Trans. on Circuits & Systems - I : Regular Papers, vol. 79, no. 7, pp. 1588-1597, July 2012. | NSC 99-2221-E-110-082-MY3 |
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| 101 | C.-H. Hsu, S.-B. Tseng, Y.-J. Hsieh, and C.-C. Wang, “One-time implantable spinal cord stimulation system prototype,” IEEE Trans. on Biomedical Circuits and Systems, vol. 5, no. 5, pp. 490-498, Oct. 2011. | NSC 99-2221-E-110-081-MY3 |
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| 100 | C.-C. Wang, C.-H. Hsu, S.-C. Liao, and Y.-C. Liu, “A wide voltage range digital I/O design using novel floating N-well Circuit,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1481-1485, Aug. 2011.(accepted, paper no. TVLSI-00400-2009R1, Apr. 2010) | NSC96-2628-E-110-19-MY3 |
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| 099 | R.-C. Kuo, T.-H. Tsai, Y.-J. Hsieh and C.-C. Wang, “A high precision low dropout regulator with nested feedback loops,” Microelectronics Journal, vol. 42, no. 7, pp. 966-971, July, 2011. | MOEA 99-EC-17-A-01-SI-104 |
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| 098 | C.-C. Wang, C.-L. Chen, G.-N. Sung, and C.-L. Wang, “A high-ffficiency DC-DC buck converter for sub-2xVDD power supply” , Microelectronics Journal, vol. 42, no. 5, pp. 709-717, May 2011. | NSC99-2221-E-110-082-MY3 |
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| 097-1 | C.-C. Wang, F. Lustenberger, Y. Massoud, W. A. Serdijn*” Guest Editorial : Special Issue on ISCAS 2009, ” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, vol. 57, no. 5, pp. 953-955, May 2010 | Download | |
| 097 | C.-C. Wang, C.-H. Hsu, G.-N. Sung, and Y.-C. Lu, “A signed array multiplier with bypassing logic,” J. of Signal Processing Systems, vol. 66, no. 2, pp. 87-92, Nov. 2010. | NSC 99-2221-E-110-081-MY3 |
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| 096 | C.-C. Wang, C.-H. Hsu, C.-C. Lee, and J.-M. Huang, “A ROM-less DDFS based on a parabolic polynomial interpolation method with an offset,” J. of Signal Processing Systems, vol. 64, no. 3, pp. 351-359, May 2010. | NSC96-2628-E-110-019-MY3 |
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| 095 | C.-C. Wang, G.-N. Sung, M.-K. Chang, and Y.-Y. Shen, “Energy-efficient double-edge triggered flip-flop,” J. of Signal Processing Systems, vol. 61, no. 3, pp. 347-352, Sep. 2010 | NSC 97-2220-E-110-009 |
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| 094 | C.-C. Wang, R.-C. Kuo, J.-W. Liu, “0.9 V to 5 V bidirectional mixed-voltage I/O buffer with an ESD protection output stage,”IEEE Trans. on Circuits & Systems - II (TCAS-II), vol. 57, no. 8, pp. 612-616, Aug. 2010. | NSC98-2220-E-110-009 |
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| 093 | G.-N. Sung, S.-C. Liao, G.-N. Sung, J.-M. Huang, Y.-C. Lu, and C.-C. Wang, “All digital frequency synthesizer using a flying adder,” IEEE Trans. on Circuits & Systems – II (TCAS-II), vol. 57, no. 8, pp. 597-601, Aug. 2010. | NSC96-2923-E-110-001-MY3 |
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| 092 | C.-C. Wang, C.-H. Hsu, and Y.-C. Liu, “A 1/2 X VDD to 3 X VDD bidirectional I/O buffer with a dynamic gate bias generator,” IEEE Trans. on Circuits & Systems - I (TCAS-I), vol. 57, no. 7, pp. 1642-1653, July 2010. | MOEA97-EC-17-A-01-S1-104 |
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| 091 | S. Ozeri, D. Shmilovitz, S. Singer, and C.-C. Wang, “Ultrasonic transcutaneous energy transfer using a continuous wave 650 kHz Gaussian shaded transmitter,” Ultrasonics, vol. 50, no. 7, pp. 666-674, June 2010. |
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| 090 | C.-C. Wang, C.-C. Huang, and U. F. Chio, “A linear LDO regulator with modified NMCF frequency compensation independent of off-chip capacitor and ESR,” Analog Integrated Circuits and Signal Processing, vol. 63, no. 2, pp. 239-244, May 2010. SCI | NSC 92-2218-E-110-001 |
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| 089 | C.-C. Wang, C.-L. Chen, R.-C. Kuo, and D. Shmilovitz, “Self-sampled all-MOS ASK demodulator for lower ISM band applications,” IEEE Trans. on Circuits & Systems - II : Brief Papers, vol. 57, no. 4, pp. 265-269, Apr. 2010. (accepted, paper no. 7280, Jan. 2010) | MOEA97-EC-17-A-01-S1-104 |
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| 088 | C.-C. Wang, G.-N. Sung, P.-C. Chen, and C.-L. Wey, “A transceiver frontend for electronic control units in FlexRay-based automotive communication systems,” IEEE Trans. on Circuits & Systems - I : Regular Paper, vol. 57, no. 2, pp. 460-470, Feb. 2010. SCI | NSC96-2628-E-110-018-MY3 |
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| 087 | C.-C. Wang, G.-N. Sung, J.-M. Huang, L.-H. Lee, and C.-P. Li, “A Low-power 2.45 GHz WPAN modulator/demodulator,” Microelectronics Journal, vol. 41, no. 2-3, pp. 150-154, Feb.-Mar. 2010. SCI | NSC98-2220-E-110-009 |
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| 086 | C.-C. Huang, T.-J. Lee, W.-C. Chang, and C.-C. Wang, “1/3 VDD to 3/2 VDD wide-range I/O buffer using 0.35-μm 3.3-V CMOS technology,” IEEE Trans. on Circuits & Systems - II : Brief Papers, vol. 57, no. 2, pp. 126-130, Feb. 2010. SCI | NSC 96-2628-E-110-19-MY3 |
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| 085 | C.-C. Wang, C.-H. Hsu, C.-C. Huang, and J.-H. Wu, “A Self-Disabled Sensing Technique for Content-Addressable Memories”, IEEE Trans. on Circuits & Systems - II : Brief Papers, vol. 57, no. 1, pp. 31-35, Jan. 2010. SCI | NSC 96-2628-E-110-19-MY3 |
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| 084 | C.-C. Wang, C.-H. Hsu, C.-C. Huang, T.-J. Lee, C.-C. Hung, Y.-H. Hsueh, and R. Hu, “High-PSR sync separator for TV signals,” Analog Integrated Circuits and Signal Processing, vol. 61, no. 3, pp. 279-286, Mar. 2009. | NSC94-2213-E-110-024 |
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| 083 | C.-C. Wang, and G.-N. Sung, “Low-power multiplier design using a bypassing technique, ” J. of Signal Processing Systems, vol. 57, no. 3, pp. 331-338, Dec. 2009. | NSC96-2928-E-110-018-MY3 |
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| 082 | C.-C. Huang, G.-L. Jhuang, and C.-C. Wang, “A high-SFDR direct digital frequency synthesizer with embedded error-compensation CMOS OTP ROM for wireless receivers,” Microwave and Optical Technology Letters, vol. 51, no. 7, pp. 1695-1699, July 2009. | NSC 96-2923-E-110-001 |
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| 081 | T.-J. Lee, T.-Y. Chang, and C.-C. Wang, “Wide-range 5.0/3.3/1.8 V I/O buffer using 0.35-um 3.3-V CMOS technology,” IEEE Trans. on Circuits & Systems - I : ?Regular Papers, vol. 56, no. 4, pp. 763-772, Apr. 2009. SCI (accepted, paper no. 6314, July 2008) | NSC96-2923-E-110-001-MY3 |
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| 080 | S.-H. Wang, C.-P. Li, C.-T. Yu, J.-M. Huang, and C.-C. Wang,“Baseband receiver design for the MBOA ultra wideband wireless personal area networks,” IEICE Trans. on Commun., vol. E92-B, no. 01, pp.143-149 , Jan. 2009. |
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| 079 | T.-J. Lee, and C.-C. Wang, “A PLL with 30% jitter reduction using separate regulators,” Inter. J. of VLSI Design, vol. 2008, Article ID : 512946, pp. 1-8, 2008 | NSC96-2923-E-110-001-MY2 |
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| 078 | J.-M. Huang, C.-C. Wang, and Y.-J. Chiu, “A CMOS opto-electronic single chip using the hybrid scheme for optical receivers,” Microwave and Optical Technology Letters, vol. 50, no. 9, pp. 2430-2434, Sep. 2008. | 95C030133 |
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| 077 | C.-C. Wang, G.-N. Sung, C.-C. Huang, C.-L. Lee, T.-H. Chen, W.-J. Lin, and R. Hu, “1.7-ns access time SRAM using variable bulk bias wordline-controlled transistors,” Journal of Circuits, Systems, and Computers (JCSC), vol. 17, no. 5, pp. 943-956, Nov. 2008 | NSC94-2213-E-110-022 |
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| 076 | C.-C. Wang, C.-C. Huang, J.-S. Liou, Y.-J. Ciou, I.-Y. Huang, C.-P. Li, Y.-C. Lee, and W.-J. Wu, “A mini-invasive long-term bladder urine pressure measurement ASIC and system,” IEEE Trans. on Biomedical Circuits and Systems, vol. 2, no. 1, pp. 44-49, Mar. 2008. | NSC94-2213-E-110-053 |
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| 075 | Y.-T. Li, C.-H. Lin, C.-C. Wang, J.-J. J. Chen, “Development of an implantable wireless biomicrosystem with impedance spectroscopy measurement and nerve stimulation functions,” International Journal of Electrical Engineering, vol. 15, no. 3, pp. 169-178, 2008. EI |
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| 074 | C.-C. Wang, C.-C. Huang, and S.-L. Tseng, “A low-power ADPLL using feedback DCO quaterly disabled in time domain,” Microelectronics Journal, vol. 39, no. 5, pp. 832-840, May, 2008. SCI | NSC96-2628-E-110-019-MY3 |
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| 073 | T.-J. Lee, C.-L. Lee, Y.-J. Chiu, C.-C. Huang, and C.-C. Wang, “All-MOS ASK demodulator for low-frequency applications,” IEEE Trans. on Circuits & Systems, Part II : EXPRESS BRIEFS (TCAS-II), vol. 55, no. 5, pp. 474-478, May 2008. SCI | NSC94-2213-E-110-053 |
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| 072 | C.-C. Wang, C.-C. Huang, C.-L. Lee, C.-C. Hung, and L.-P. Lin, “A single-chip CMOS IF-band converter design for DVB-T receivers,” Microelectronics Journal, vol. 39, no. 1, pp. 117-129, Jan. 2008. SCI | NSC94-2213-E-110-022 |
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| 071 | C.-C. Wang, T.-J. Lee, U. F. Choi, Y.-T. Hsiao, and J.-J. J. Chen, “A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants,” Microelectronics Journal, vol. 39, no. 1, pp. 130-136, Jan. 2008. SCI | NHRI-EX95-9319EI |
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| 070 | C.-C. Wang, C.-C. Huang, J.-M. Huang, C.-Y. Chang. And C.-P. Li, “ZigBee 868/915 MHz modulator/demodulator for wireless personal area network,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 7, pp. 936-939, July 2008. SCI | NSC94-2213-E-110-024 |
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| 069 | C.-C. Wang, C.-C. Huang, C.-L. Lee, L.-P. Lin, and Y.-L. Tseng, “70 dB dynamic range CMOS wideband digital variable gain amplifier for AGC in DVB-T/H receivers,” Journal of Circuits Systems and Signal Processing, vol. 27, no. 3, pp. 367-379, June 2008. SCI | NSC94-2213-E-110-022 |
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| 068 | C.-C. Wang, G.-N. Sung, and P.-L. Liu, “Power-aware design of an 8-bit pipelining ANT-based CLA using data transition detection,” Journal of Signal Processing Systems, vol. 52, no 2, pp. 127-135, Aug. 2008. SCI | NSC92-2220-E-110-001 |
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| 067 | C.-C. Wang, C.-C. Huang, C.-L. Lee, and T.-W. Cheng, “A low power high-speed 8-bit pipelining CLA design using dual threshold voltage domino logic,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 5, pp. 594-598, May 2008. SCI | NSC94-2213-E-110-022 |
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| 066 | S.-H. Wang, C.-P. Li, and C.-C. Wang, “An interference cancellation scheme for carrier frequency offsets compensation in the uplink of OFDMA systems,” Inter. J. of Electrical Engineering, vol. 14, no. 5, pp. 339-347, Oct. 2007. |
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| 065 | C.-C. Wang, G.-N. Sung, J.-M. Huang, and L.-P. Lin, “An 80 MHz PLL with 72.7-ps peak-to-peak jitter,” Microelectronics Journal, vol. 38, issues 6-7, pp. 716-721, June-July 2007. SCI | NSC94-2213-E-110-022 |
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| 064 | C.-C. Wang, C.-L. Lee, W.-J. Lin, “A 4-Kb low power SRAM design with negative word-line scheme,” IEEE Trans. on Circuits and Systems - I: Fundamental Theory and Applications, vol. 54, no. 5, pp. 1069-1076, May 2007. SCI | NSC94-2213-E-110-022 |
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| 063 | C.-C. Wang, T.-J. Lee, C.-C. Li, and R. Hu, “Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator,” Microelectronics Journal, vol. 38, no. 2, pp. 197-202, Feb. 2007. SCI | NSC91-2218-E-110-001 |
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| 062 | C.-C. Wang, C.-L. Lee, C.-Y. Hsiao, and J.-F. Huang, “Clock-and-data recovery design for LVDS transceiver used in LCD panels,” IEEE Trans. on Circuits and Systems - II, vol. 53, no. 11, pp. 1318-1322, Nov. 2006. SCI | NSC 92-2220-E-110-001 |
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| 061 | C.-C. Wang, J.-M. Huang, Y.-L. Tseng, W.-J. Lin, and R. Hu, “Phase-adjustable pipelining ROM-less direct digital frequency synthesizer with a 41.66 MHz Output Frequency,” IEEE Trans. on Circuits and Systems - II, vol. 53, no. 10, pp. 1143-1147, Oct. 2006. SCI | NSC 92-2220-E-110-001 |
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| 060 | C.-C. Wang, T.-J. Lee, C.-C. Li, and R. Hu, “An all-MOS high linearity voltage-to-frequency converter chip with 520 KHz/V sensitivity,” IEEE Trans. on Circuits and Systems - II, vol. 35, no. 8, pp. 744-747, Aug. 2006. SCI | NHRI-EX93-9319EI |
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| 059 | C.-C. Wang, T.-J. Lee, H. K. Lo, S.-P. Lin, and R. Hu, “High-Sensitivity and High-Mobility Compact DVB-T Receiver for In-Car Entertainment,” IEEE Trans. on Consumer Electronics, vol. 52, no. 1, pp. 21-25, Feb. 2006. SCI | NSC 94-2213-E-110-024 |
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| 058 | C.-C. Wang, T.-J. Lee, Y.-T. Hsiao, U. F. Chio, C.-C. Huang, J.-J. J. Chen, and Y.-H. Hsueh, “A multi-parameter implantable micro-stimulator SOC,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 12, pp. 1399-1402, Dec. 2005. SCI | NSC 92-2218-E-110-001 |
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| 057 | C.-C. Wang, C.-L. Lee, Y.-L. Tseng, C.-S. Chen, and R. Hu, “Low-power small-area digital I/O cell,” IEEE Trans. on Circuits and Systems - II, vol. 52, no. 8, pp. 508-511, Aug. 2005. SCI | NSC 92-2220-E-110-001 |
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| 056 | C.-C. Wang, J.-M. Huang, H.-C. Cheng, and R. Hu, “Switched-current 3-bit CMOS 4.0 MHz wideband random signal generator,” IEEE J. of Solid-State Circuits, vol. 40, no. 6, pp. 1360-1365, June 2005. SCI | NSC 91-2218-E-110-001 |
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| 055 | C.-C. Wang, C.-L. Lee, and M.-K. Chang, “Low-cost video decoder with 2D2L comb filter for NTSC digital TVs,” IEEE Trans. on Consumer Electronics, vol. 51, no. 2, pp. 694-698, May 2005. SCI | NSC 92-2220-E-110-001 |
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| 054 | C.-C. Wang, Y.-L. Tseng, and C.-C. Chiu, “A temperature-insensitive self-recharging circuitry used in DRAMs,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 3, pp. 405-408, Mar. 2005. SCI | NSC93-2220-E-110-001 |
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| 053 | C.-C. Wang, J.-M. Huang, and H.-C. Cheng, “A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers,” IEEE Trans. on Consumer Electronics, vol. 51, no. 1, pp. 28-32, Feb. 2005. SCI | NSC92-2220-E-110-001 |
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| 052 | C.-K. Liang, J.-J. J. Chen, C.-L. Chung, C.-L. Cheng and C.-C. Wang, “An implantable bi-directional wireless transmission system for transcutaneous biological signal recording,” Physiological Measurement, vol. 26, no. 1, pp. 83-97, Feb. 2005. SCI | NHRI-EX93-9319EI |
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| 051 | Y. T. Li,C. H. Chang, J.-J. Jason Chen, C.-C. Wang, and C. K. Liang, “Development of wireless biomicrosystem for measuring electrode-tissue impedance,” Journal of Medical and Biological Engineering, vol. 25, no. 3, pp. 99-105, Sep. 2005. EI | NHRI-EX93-9319EI |
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| 050 | C.-C. Wang, Y.-L. Tseng, H.-C. She, and R. Hu, “A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 12, pp. 1377-1381, Dec. 2004. SCI | NSC92-2220-E-110-001 |
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| 049 | C.-C. Wang, T.-J. Lee, Y.-H. Hsueh, Y.-T. Hsiao, and U F. Chio, “Baseband design of a wireless transceiver for implantable neural interface,” International Journal of Chinese Institute of Electrical Engineering, vol. 11, no. 4, pp. 355-360, Nov. 2004. | NHRI-EX93-9319EI |
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| 048 | C.-C. Wang, Y.-L. Tseng, H.-Y. Leo, and R. Hu, ”A 4-Kb 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 901-908, Sep. 2004. SCI | NSC89-2215-E-110-014 |
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| 047 | C.-C. Wang, Y.-L. Tseng, H.-C. She, C.-C. Li, and R. Hu, “A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 895-900, Sep. 2004. SCI | NSC92-2220-E-110-001 |
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| 046 | C.-C. Wang, P.-M. Lee, and K.-L. Chen, “An SRAM Design Using Dual Threshold Voltage Transistors and Low-Power Quenchers,” IEEE J. of Solid-State Circuits, vol. 38, no. 10, pp. 1712-1720, Oct. 2003. SCI | NSC89-2218-E-110-014 |
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| 045 | C.-C. Wang, Y.-L. Tseng, P.-M. Lee, R.-C. Lee, and C.-J. Huang, “A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic,” IEEE Trans. on Circuits and Systems - I: Fundamental Theory and Applications, vol. 50, no. 9, pp. 1208-1216, Sep. 2003. SCI, EI | NSC89-2218-E-110-014 |
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| 044 | C.-C. Wang, P.-M. Lee, C.-F. Wu, and H.-L. Wu, “High fan-in dynamic CMOS comparators with low transistor count,” IEEE Trans. on Circuits and Systems - I: Fundamental Theory and Applications, vol. 50, no. 9, pp. 1216-1220, Sep. 2003. SCI, EI | NSC89-2218-E-110-014 |
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| 043 | C.-C. Wang, Y.-H. Hsueh, and Y.-P. Chen, “An area-saving decoder structure for ROMs,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp. 581-589, Aug. 2003. SCI, EI | NSC89-2218-E-110-015 |
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| 042 | C.-C. Wang, P.-M. Lee, J.-J. Wang, and C.-J. Huang, “Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp. 737-740, Aug. 2003. SCI | NSC89-2218-E-110-014 |
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| 041 | C.-C. Wang, Y.-H. Hsueh, and C.-J. Huang, “A fast bipolar-valued inner product processor chip for associative memory networks,” IEEE Trans. on Circuits and Systems - I: Fundamental Theory and Applications, vol. 50, no. 7, pp. 958-961, July 2003. SCI, EI | NSC88-2219-E-110-001 |
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| 040 | C.-C. Wang, Y.-H. Hseuh, C.-S. Chen, and J.-F. Huang, “A low-cost plasma display panel data dispatcher for image enhancement,” IEEE Trans. on Consumer Electronics, vol. 48, no. 4, pp. 997-1003, Nov. 2002 SCI, EI |
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| 039 | C.-C. Wang, Y.-H. Hsueh, Y.-T. Chien, and Y.-P. Chen, “Design of an inter-plane circuit for clocked PLAs,” VLSI Design, vol. 14, no. 4, pp. 373-381, June 2002. SCI, EI | NSC89-2215-E-110-017 |
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| 038 | C.-C. Wang, Y.-H. Hsueh, H.-L. Wu, and C.-F. Wu, “A fast dynamic 64-bit comparator with small transistor count,” VLSI Design, vol. 14, no. 4, pp. 389-395, June 2002. SCI, EI | NSC89-2215-E-110-017 |
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| 037 | C.-C. Wang, P.-M. Lee, and C.-J. Huang, “Improved Design of C2PL 3-2 compressors for Inner Product Processing,” VLSI Design, vol. 14, no. 4, pp. 383-388, June 2002. SCI, EI | NSC87-2215-E-110-010 |
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| 036 | C.-J. Huang, C.-C. Wang, and C.-F. Wu, “Image processing techniques for wafer defect cluster identification,” IEEE Design and Test of Computer, vol. 19, no. 2, pp. 44-48, March-April 2002. | NSC88-2219-E-110-001 |
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| 035 | C.-C. Wang, Y.-H. Hsueh, and S.-K. Huang, “An embedded low transistor count 8-bit analog-to-digital converter using a binary searching method,” VLSI Design, vol. 14, no. 2, pp. 193-202, March 2002. SCI, EI | NSC89-2215-E-110-017 |
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| 034 | C.-C. Wang, H.-L. Wu, and R.-C. Lee, “Man-machine interface modules for wireless ARM-based handsets (1/3),” Engineering, Science, and Technology Bulletin, vol. 58, pp. 156-161, Oct. 2001. | NSC89-2218-E-110-014 |
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| 033 | C.-C. Wang, C.-F. Tsai, and Y.-T. Chien, “Pattern recognition by high-capacity polynomial bidirectional hetero-associative network,” Journal of Information Science and Engineering, vol. 17, no. 2, pp. 313-324, Mar. 2001. SCI, EI | NSC88-2219-E-110-001 |
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| 032 | C.-J. Huang, W. K. Lai, C.-C. Wang, Y.-J. Jin, and H. W. Chen, “A ratioed channel assignment scheme for initial and handoff calls in mobile cellular systems,” Computer Communications, vol. 24, no. 3-4, pp. 308-318, Feb. 2001. SCI |
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| 031 | C.-C. Wang, C.-J. Huang, and P.-M. Lee, “Design and analysis of digital ratioed compressors for inner product processing,” VLSI Design, vol. 11, no. 4, pp. 353-361, Dec. 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 030 | C.-C. Wang, C.-J. Huang, and I.-Y. Chang, “Design and analysis of Radix-8/4/2 64b/32b integer divider using COMPASS Cell library,” VLSI Design, vol. 11, no. 4, pp. 331-338, Dec. 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 029 | C.-C. Wang, C.-J. Huang, and Y.-P. Chen, “Design of an inner-product processor for hardware realization of multi-valued exponential bidirectional associative memory,” IEEE Trans. of Circuits and Systems, Part II : Analog and Digital Signal Processing, vol. 47, no. 11, pp. 1271-1278, Nov. 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 028 | C.-C. Wang, C.-J. Huang, and S.-M. Hwang, “A deterministic capacity-finding method for multi-valued exponential BAM,” IEEE Trans. on Systems, Man, and Cybernetics, vol. 30, no. 6, pp. 817-819, Nov. 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 027 | C.-C. Wang, P.-M. Lee, Y.-L. Tseng, and C.-F. Wu, “A low-cost quadrature decoder/counter interface integrated circuit for AC induction motor server control,” Inter. J. of Electronics, vol. 87, no. 9, pp. 1053-1063, Sep. 2000. SCI | NSC87-2215-E-110-010 |
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| 026 | C.-C. Wang and C.-F. Tsai, “Analysis of practical expectation of the capacity of PBHC with fault tolerance,” IEEE Trans. on Circuits and Systems - I: Fundamental Theory and Applications, vol. 47, no. 8, pp. 1271-1275, Aug. 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 025 | C.-C. Wang, Y.-T. Chien, and Y.-P. Chen, “A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop,” VLSI Design, vol. 11, no. 2, pp. 107-113, June 2000. SCI, EI | NSC87-2215-E-110-010 |
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| 024 | C.-C. Wang, P.-M. Lee, and C.-J. Huang, “Three alternative architecture of digital ratioed compressor design with application to inner product processing,” IEE proceedings - Computers and Digital Techniques, vol. 147, no. 2, pp. 65-74, March 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 023 | C.-C. Wang, C.-J. Huang, G.-C. Lin, and C.-F. Wu, “Cell-based implementation of Radix-4/2 64b dividend 32b divisor signed integer divider using the COMPASS cell library,” IEE proceedings - Computers and Digital Techniques, vol. 147, no. 2, pp. 109-115, March 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 022 | C.-C. Wang, C.-J. Huang, and K.-C. Tsai, “A 1.0 GHz 0.6-µm 8-bit carry lookahead adder using PLA-styled all-N-transistor logic,” IEEE Trans. of Circuits and Systems, Part II : Analog and Digital Signal Processing, vol. 47, no. 2, pp. 133-135, Feb. 2000. SCI | NSC88-2219-E-110-001 |
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| 021 | C.-C. Wang, C.-F. Wu, R.-T. Hwang, and C.-H. Kao, “Single-ended SRAM with high test coverage and short test time,” IEEE J. of Solid-State Circuits, vol. 35, no. 1, pp. 114-118, Jan. 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 020 | C.-C. Wang, and C.-F. Tsai, “Fuzzy data processing using polynomial bidirectional hetero-associative network,” Information Sciences, vol. 125, no. 4, pp. 167-179, 2000. SCI, EI | NSC88-2219-E-110-001 |
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| 019 | C.-C. Wang and C.-F. Tsai, “Polynomial bidirectinal hetero-correlator,” Electronics Letters, vol. 35, no. 23, pp. 2039-2041, Nov. 1999. SCI, EI | NSC89-2219-E-110-001 |
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| 018 | C.-F. Tsai, and C.-C. Wang, “The study of an architecture of WWW software of multimedia computer assembly,” Bulletin of National Pingtung University of Science and Technology, vol. 8, no. 3, pp. 237-250, Sep. 1999. |
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| 017 | C.-C. Wang, C.-F. Wu, S.-H. Chen, and C.-H. Kao, “In-sawing-lane multi-level BIST for known good dies of LCD drivers,” Electronics Letters, vol. 35, no. 8, pp. 1543-1544, Sep. 1999. SCI, EI | NSC87-2215-E-110-010 |
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| 016 | C.-C. Wang, C.-F. Wu, R.-T. Hwang, and C.-H. Kao, “A low-power high-speed dynamic PLA circuit configuration for single-clock CMOS,” IEEE Trans. on Circuits and Systems, Part I : Fundamental Theory and Applications, vol. 46, no. 7, pp. 857-861, July 1999. SCI, EI | NSC87-2215-E-110-010 |
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| 015 | C.-C. Wang, C.-F. Wu, and K.-C. Tsai, “1 GHz 64-bit High-Speed Comparator Using ANT Dynamic Logic with Two-Phase Clocking,” IEE proceedings - Computers and Digital Techniques, vol. 145, no. 6, pp. 433-436, Nov. 1998. SCI | NSC86-2622-E-009-009 |
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| 014 | C.-F. Wu, C.-C. Wang, R.-T. Hwang, and C.-H. Kao, “Dynamic NOR-NOR PLA Design with IDDQ Testability,” Inter. J. of Elctronics, vol. 86, no. 1, pp. 79-85, Jan. 1999. SCI, EI | NSC86-2215-E-110-013 |
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| 013 | C.-C. Wang, and H.-S. Don, “The majority theorem of centralized multiple BAMs netwroks,” Information Sciences, vol. 110, no. 3-4, pp. 179-193, Oct. 1998. SCI | NSC84-0408-E-110-003 |
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| 012 | C.-C. Wang, C.-F. Tsai, and J.-P. Lee, “Analysis of radix searching of exponential bidirectional associative memory,” IEE proceedings - Computers and Digital Techniques, vol. 145, no. 4, pp. 279-285, July 1998. SCI | NSC83-0404-E-110-014 |
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| 011 | C.-C. Wang and C.-R. Tsai, “Data compression by the recursive algorithm of exponential bidirectional associative memory,” IEEE Trans. on System, Man, and Cybernetics, Part B: Cybernetics, vol. 28, no. 2, pp. 125-134, April 1998. SCI | NSC83-0408-E-110-014 |
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| 010 | C.-C. Wang and C.-L. Fan, “Digitial Design of Discrete Exponential Bidirectional Associative Memory,” Journal of VLSI Signal Processing, vol. 15, no. 3, pp. 247-257, Mar. 1997. SCI | NSC84-0408-E-110-003 |
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| 009 | C.-C. Wang, “Practical Capacity and Attraction Radix Analysis of Exponential Bidirectional Associative Memory,” Journal of Information Science and Engineering, vol. 12, no. 4, pp. 511-523, Dec. 1996. | NSC84-0408-E-110-003 |
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| 008 | C.-C. Wang and Y.-L. Fan, “Low-power greedy state pair grouping algorithm and power reduction estimation for finite state machine,” The Proceedings of the National Science Council, Part A: Physical Science and Engineering, vol. 20, no. 6, pp. 641-650, Nov. 1996. SCI | NSC85-2215-E-110-018 |
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| 007 | C.-C. Wang, S.-M. Hwang, and J.-P. Lee, “Capacity analysis of the asymptotically stable multi-valued exponential bidirectional associative memory,” IEEE Trans. on Systems, Man, and Cybernetics Part B: Cybernetics, vol. 26, no. 5, pp. 733-743, Oct. 1996. SCI | NSC83-0404-E-110-014 |
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| 006 | C.-C. Wang and J.-P. Lee, “The decision making properties of discrete multiple exponential bidirectional associative memories,” IEEE Trans. on Neural Networks, vol. 6, no. 4, pp. 993-999, July 1995. SCI | NSC82-0113-E-011-092-T |
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| 005 | C.-C. Wang and H.-S. Don, “An analysis of high-capacity discrete exponential BAM,” IEEE Trans. on Neural Networks, vol. 6, no. 2, pp. 492-496, Mar. 1995. SCI |
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| 004 | H.-S. Don and C.-C. Wang, “Belief combination by a potential model,” Journal of Engineering, National Chung Hsing University, vol. 6, no. 1, pp. 13-23 , Jan. 1995. | NSC83-0408-E-110-015 |
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| 003 | C.-C. Wang and H.-S. Donl, “A modified measure for fuzzy subsethood,” Information Sciences, vol. 79, no. 3 & 4, pp. 223-232, July 1994. SCI |
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| 002 | C.-C. Wang and H.-S. Don, “A polar model for evidential reasoning,” Information Sciences, vol. 77, no. 3 & 4, pp. 195-226, 1994. SCI |
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| 001 | C.-C. Wang and H.-S. Don, “A robust continuous model for evidential reasoning,” Journal of Intelligent & Robotic Systems, 9: pp. 1-25, 1994. SCI |
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